Tuning system for a digital satellite receiver with fine tuning provisions

ABSTRACT

An economical tuning system for a digital satellite television receiver includes a phase locked loop (PLL) tuning control IC of the which is normally used in a tuning system of a conventional terrestrial broadcast or cable television reciever to control the frequency of the local oscillator (LO). Unfortunately, the PLL IC is only capable of changing the frequency of the LO in relatively large steps. As a result, the operation of a carrier recovery loop which demodulates the digitally encoded IF signal produced by the tuner may be interrupted during a fine tuning mode because the carrier recovery loop may not be able to track frequency changes of the LO. To reduce such possibility, the integrator filter associated with the PLL IC is modified to decrease the rate of change of the LO frequency during the fine tuning mode.

CROSS REFERENCE TO A RELATED APPLICATION

This application is a continuation-in-part of U.S. patent applicationSer. No. 08/467,097, entitled "Tuner For A Digital Satellite Receiver",filed on Jun. 6, 1995 for Michael A. Pugel and Kurt J. Richter.

FIELD OF THE INVENTION

The invention concerns a tuning system for a satellite receiver,especially one capable of receiving and processing television signalstransmitted in digital form.

BACKGROUND OF THE INVENTION

Satellite television receiving systems usually comprise an "outdoorunit" including a dish-like receiving antenna and a "block" converter,and an "indoor unit" including a tuner and a signal processing section.The block converter converts the entire range ("block") of relativelyhigh frequency RF signals transmitted by a satellite to a moremanageable, lower range of frequencies.

In a conventional satellite television transmission system televisioninformation is transmitted in analog form and the RF signals transmittedby the satellite are in the C (e.g., 3.7 to 4.2 gHz) and Ku (e.g., 11.7to 14.2 gHz) bands. The RF signal received from the satellite by theantenna of the receiving system are converted by the block converter tothe L band (e.g., 900 to 2000 mHz). An RF filter section of the tuner ofthe indoor unit selects the one of the RF signals received from theblock converter corresponding to the selected channel, and a mixer/localoscillator section of the tuner converts the selected RF signal to alower, intermediate frequency (IF) range for filtering and demodulation.Typically, the IF frequency range has a nominal center frequency of479.5 mHz. Analog satellite television systems typically employ FMmodulation, and a baseband video signal is readily obtained from the479.5 mHz IF signal by an FM demodulator after filtering by an IFfilter. A relatively simple surface acoustic wave (SAW) device canprovide adequate filtering in an analog satellite television receiver.

In newer satellite television systems, such as the DirecTv™ operated bythe Hughes Corporation of California, television information istransmitted in digital form. The RF signals are transmitted by thesatellite in the Ku band, and are converted by the block converter tothe L band. The frequency range of the RF signals transmitted by thesatellite is somewhat smaller (e.g., between 12.2 and 12.7 gHz) thanthat for the analog satellite television system, and the frequency rangeof RF signals produced by the block converter is accordingly somewhatsmaller (e.g., between 950 and 1450 mHz).

As in the analog satellite television receiving systems, the RF signalcorresponding to the selected channel has to be reduced in frequency toan IF frequency range for filtering and demodulation. In a digitalsatellite receiver, in addition to the normal IF filtering for selectingthe desired RF signal and rejecting unwanted RF signals, it is desirablethat the IF filter perform what is known as "symbol shaping" to reducedecoding errors due to "inter-symbol interference" caused by bandwidthlimitations. However, the symbol shaping function cannot readily beperformed at relatively high IF frequencies, such as at the 479.5 mHz IFfrequency employed in an analog satellite television receiver,especially when the IF filter comprises a SAW device. As a result, arelatively expensive separate digital filter is required. It is possibleto employ a second conversion stage to convert a relatively highfrequency (e.g., 479.5 mHz) first IF signal to a second, lower frequency(e.g., less than 100 mHz) IF signal prior to IF filtering. However, thesecond conversion stage adds undesirable cost to the receiver.

It is also desirable that the tuning system of the digital satellitetelevision receiver be capable of being constructed utilizing componentswhich are already commercially available and therefore relativelyinexpensive. Specifically, in this regard it is desirable that thetuning system be capable of being constructed utilizing a commerciallyavailable integrated circuit (IC) which incorporates a phase locked loop(PLL) for controlling the frequency of the local oscillator. Since alarge number of tuner PLL ICs for conventional television receiverswhich receive and process conventional terrestrial broadcast and cabletelevision signals are already widely available, it is particularlydesirable that the tuning system of a digital satellite televisionreceiver be capable of being constructed utilizing such a conventionaltuner PLL IC.

A single conversion tuner for a digital satellite television receiverwhich permits the use of a SAW filter with symbol shaping capabilitiesand the use of the type of PLL IC which is conventionally employed interrestrial broadcast and cable tuning systems is described in theabove-identified U.S. patent application. Basically, these two desirableattributes are accomplished by: (1) selecting an IF center frequency inthe order of the difference (e.g., 140 mHz) between the highestfrequency of the RF signal received from the block converter (e.g., 1450mHz) and highest local oscillator frequency (e.g., in the order of 1300mHz) available when employing a conventional terrestrial broadcast andcable tuning control PLL IC; and (2) utilizing a local oscillator signalwith a frequency range which is lower then, rather than higher than, thefrequency range of the received RF signals.

SUMMARY OF THE INVENTION

A single conversion tuning system for a digital satellite televisionreceiver of the type just described performs very satisfactorily undermost operating conditions. However, the present inventors havediscovered that due to the characteristics of the block converter of theoutdoor unit, the nature of the digital signal demodulation process, andcertain limitations of the terrestrial broadcast and cable PLL tuningcontrol IC, the reproduced image may be occasionally interrupted.

More specifically, the conversion stage of the block converter of theoutdoor unit usually includes a local oscillator which is not stabilizedagainst variations of temperature and age. The result is that thefrequency of the local oscillator signal of the block converter changes,causing a corresponding change of the frequencies of the carrier signalsof the RF signals received by the tuner of the indoor unit. As aconsequence, the frequency of the IF signal produced by the tuner alsochanges from its nominal value. If the frequency of the IF signalchanges too far from its nominal value, the digital signals modulated onthe IF signal cannot be properly demodulated and the information theyrepresent cannot be properly reconstructed. To overcome this problem,the frequency of the local oscillator of the tuner of the indoor unitcan be changed during a fine tuning operation in order to compensate forchanges in the frequency of the IF signal. If the local oscillatorfrequency is changed in small enough steps, the operation of the digitaldemodulator can track the changes and the digital signals will continueto be properly demodulated during the fine tuning operation. However, ifthe frequency of the local oscillator signal is changed in steps whichare too large, the operation of the digital demodulator may not be ableto follow the changes and the digital signals may not be properlydemodulated during the fine tuning operation. Unfortunately, PLL ICsconventionally employed in terrestrial broadcast and cable tuningsystems typically provide for changes of the local oscillator frequencyin relatively large steps, e.g., in the order of 62.5 kHz. Accordingly,the use of such a conventional terrestrial tuning control PLL IC in adigital satellite television receiver may result in the interruption ofthe video and audio responses.

In accordance with an aspect of the invention, in a preferred embodimentof the invention, in which the tuner of a digital satellite televisionreceiver comprises a single conversion stage utilizing a conventionalterrestrial tuning control PLL IC for controlling the local oscillatorfrequency, the speed at which of the PLL arrangement controls thefrequency of the local oscillator signal is reduced during a fine tuningmode. This enables the digital data demodulator to more readily trackthe frequency changes of the IF signal during the fine tuning mode, andthereby reduces the possibility of interruptions of the video and audioresponses.

This and other aspects of the invention will be described in detail withreference to the accompanying Drawing.

BRIEF DESCRIPTION OF THE DRAWING

In the Drawing:

FIG. 1 is a block diagram of a digital satellite television receiverincluding a tuning system which is constructed in accordance with anaspect of the invention:

FIG. 2 includes a block diagram of a phase locked loop tuning controlintegrated circuit used in the tuning system shown in FIG. 1 and aschematic diagram of a circuit implementation of a controllable phaselocked loop filter which is constructed in accordance with anotheraspect of the invention;

FIG. 3 is a flow chart of a microprocessor control program for thetuning system shown in FIG. 1 in accordance with another aspect of theinvention;

FIG. 4 is a block diagram of a digital data demodulator for use in thesatellite receiver shown in FIG. 1 and useful in understanding a problemsolved in accordance with an aspect of the invention; and

FIG. 5 shows a graphical representations of amplitude versus frequencyresponse characteristics associated with the controllable phase lockedloop filter shown in FIG. 2.

In the various Figures, the same or similar reference designations areused to identify the same or similar elements.

DETAILED DESCRIPTION OF THE DRAWING

The invention will be described with reference to a digital satellitetelevision system in which television information is transmitted inencoded and compressed form in accordance with a predetermined digitalcompression standard, such as MPEG. MPEG is an international standardfor the coded representation of moving picture and associated audioinformation developed by the Motion Pictures Expert Group. The DirecTv™satellite television transmission system operated by the HughesCorporation of California is such a digital satellite televisiontransmission system.

In the transmitter, the television information is digitized, compressedand organized into a series or stream of data packets corresponding torespective video and audio portions of the television information. Thedigital data is modulated on to a RF carrier signal in what is known asQPSK (Quaternary Phase Shift Keying). modulation and the RF signal istransmitted to a satellite in earth orbit, from which it isretransmitted back to the earth. In QPSK modulation, the phases of twoquadrature phase signals, I and Q, are controlled in response to thebits of respective digital data streams. For example, the phase is setto 0 degrees (°) in response to a low logic level ("0"), and the phaseis set to 180° in response to a high logic level ("1"). The phase shiftmodulated I and Q signals are combined and the result transmitted as aQPSK modulated RF carrier signal. Accordingly, each cycle of themodulated QPSK carrier indicates one of four logic states, i.e., 00, 01,10 and 10.

A satellite typically includes a number of transponders for receivingand retransmitting respective modulated RF carriers. In a conventionalterrestrial television system, each RF carrier or "channel" containsinformation for only one television program at a time. Accordingly, toview a program, only the corresponding RF signal needs to be selected.In a digital satellite television system, each modulated RF carriercarries information for several programs simultaneously. Each programcorresponds to groups of video and audio packets which are identified bya unique header appended to the packets which identifies the program.Accordingly, to view a program, both the corresponding RF signal and thecorresponding packets need to be selected.

In the digital satellite television receiver shown in FIG. 1; RF signalsmodulated with digital signals representing video and audio informationwhich have been transmitted by a satellite (not shown) are received by adish-like antenna 1. The relatively high frequency received RF signals(e.g., in the Ku frequency range between 12.2 and 12.7 gHz) areconverted by a block converter 3, including a RF amplifier 3-1, a mixer3--3 and an oscillator 3-5, to relatively a lower frequency RF signals(e.g., in the L band between 950 and 1450 mHz). Amplifier 3-1 is a "lownoise" amplifier and is therefore block converter 3 is often referred toby the initials "LNB" for "low noise block converter". Antenna 1 and LNB3 are included in a so called "outdoor unit" 5 of the receiving system.The remaining portion of the receiver is included in a so called "indoorunit" 7.

Indoor unit 7 includes a tuning system 9 for selecting the RF signalWhich contains the packets for the desired program from the plurality ofRF signals received from outdoor unit 5 and for converting the selectedRF signal to a corresponding lower, intermediate frequency (IF) signal.The present invention is concerned with the construction of tuningsystem 9 and will be described in detail below.

The remaining portion Of indoor unit 7 demodulates, decodes anddecompresses the digital information carried in QPSK modulation form bythe IF signal to produce streams of digital video and audio samplescorresponding to the desired program, and, thereafter, converts thedigital sample streams to respective analog video and audio signalssuitable for reproduction or recording. More specifically, a QPSKdemodulator 11 demodulates the IF signal to produced two pulse signalsIP and QP which contain respective streams of data bits corresponding tothe data represented by the phase shift modulated I and Q signalsgenerated in the transmitter. A decoder 13 organizes the bits of the IPand QP signals into data blocks, corrects transmission errors in thedata blocks based on error codes which have been embed in thetransmitted data at the transmitter, and reproduces the transmitted MPEGvideo and audio packets. The video and audio packets are routed by atransport unit 15 to respective video and audio sections of a dataprocessing unit 17 where they are decompressed and converted torespective analog signals. A microprocessor 19 controls the operation ofvarious sections of indoor unit 7. However, only the control signalsgenerated and received by microprocessor 19 with which the invention isdirectly concerned are indicated in FIG. 1.

The digital satellite television receiver described so far is similar tothe RCA.sup.™ type DSS.sup.™ digital satellite system televisionreceiver commercially available from Thomson Consumer Electronics, Inc.of Indianapolis, Ind.

As noted earlier the present invention is concerned with theconstruction of tuning system 9. Tuning system 9 receives the RF signalprovided by LNB 3 at an input 901. The RF input signals are filtered bya wideband filter 903, amplified by an RF amplifier 905, and filtered bya tunable bandpass filter 907. Tunable bandpass filter (BPF) 907 selectsthe desired RF signal and rejects unwanted RF signals. The resultant RFsignal is coupled to a first input of a mixer 909. A local oscillatorsignal produced by a local oscillator (LO) 911 is coupled to a secondinput of mixer 909. The output of mixer 909 is amplified by an amplifier913 and coupled to the input of an IF filter 915 comprising a SAWdevice. The output of IF filter 915 is coupled to output 917 of tuningsystem 9.

The frequency of LO 911 is controlled by a phase locked loop (PLL)arrangement 919 comprising a PLL integrated circuit (IC) 921, anexternal frequency reference crystal 923 and an external filter network925. The frequency of the LO signal is controlled by PLL 919 inaccordance with data generated by a microprocessor 19. Details of PLL919 are shown in FIG. 2.

As is shown in FIG. 2, the PLL IC 921 includes a "prescalar" frequencydivider 921-1 for dividing the frequency of the LO signal followed by aprogrammable frequency divider (÷N) 921-3. PLL IC 921 also includes anamplifier 921-5, which in combination with external crystal 923,comprises a reference frequency oscillator. The output of the referencefrequency oscillator is coupled to the input of a reference frequencydivider (÷R) 921-7. The output signals of programmable divider (÷N)921-3 and reference divider (÷R) 921-7 are coupled to respective inputsof a phase detector 921-9. The output signal of phase detector 921-9 isan error signal which represents the frequency and phase differencesbetween the frequency divided version of the LO signal produced at theoutput of programmable divider (÷N) 921-3 and the reference signalproduced at the output of reference divider (÷R) 921-7. The error signalcontains pulses which have either a relative positive polarity or arelatively negative polarity depending on the sense of the phase andfrequency differences between the input signals of phase detector 921-9and a variable duration which depends on the magnitude of the phase andfrequency differences. The error signal is coupled to an amplifier921-11, which together with external filter network 925, comprises aloop filter 927, for filtering the error signal to produce a tuningcontrol voltage for LO 911. The tuning control voltage also controlstunable bandpass filter 907. Loop filter 927 is constructed inaccordance with an aspect of the invention and will be described indetail below.

In operation, the frequency of the LO signal is controlled in responseto the tuning voltage until the frequency and phase of the frequencydivided version of the LO signal produced at the output of programmabledivider (÷N) 921-3 are substantially equal to the frequency and phase ofthe reference signal produced at the output of reference divider (÷R)921-7. At that point, the phase locked loop is "locked" and thefrequency of the LO signal is proportionally related to the frequency ofthe reference frequency signal produced by reference frequency divider(÷R) 921-7 by the programmable division factor (N) of programmabledivider (÷N) 921-3. Programmable division factor N is controlled inresponse to data generated by microprocessor 19 in order to control theLO frequency.

For cost reasons, it is desirable that tuning system 9 have thefollowing three characteristics: (1) comprise only a single conversionstage prior to the IF filter stage; (2) provide an IF signal with a lowenough frequency to allow a SAW device to be used for so called "digitalsymbol shaping", as well as normal IF filtering; and (3) be capable ofbeing constructed utilizing a PLL tuning control IC conventionally usedfor broadcast and cable receivers. Basically, these goals areaccomplished by: (1) selecting an IF center frequency to be in the orderof the difference (e.g., 140 mHz) between the highest frequency of theRF signal received from the block converter (e.g., 1450 mHz) and highestlocal oscillator frequency (e.g., in the order of 1300 mHz) available byutilizing a conventional terrestrial broadcast and cable tuning controlPLL IC; and (2) utilizing a local oscillator signal with a frequencyrange which is lower than, rather than higher than, the frequency rangeof the received RF signals. In the exemplary tuning system the centerfrequency of the IF signal is 140 mHz. However other IF frequencies arepossible utilizing the guidelines set forth above.

A relatively low IF center frequency, e.g., in the order of 140 mHz,allows a single conversion tuner rather than a more expensive doubleconversion tuner to be used prior to the IF filter section. It alsoallows a SAW device which provides so called "digital symbol shaping",as well as normal IF filtering, to be used. In a digital transmissionsystem, what is known as "digital symbol shaping" is performed in thetransmitter to reduce inter-symbol interference due to transmissionbandwidth limitations. It is also desirable to perform digital symbolshaping in the receiver to complement the digital symbol shapingperformed in the transmitter. Moreover, it is desirable that the IFfilter provide for symbol shaping, as well as the normal IF filteringfunction, so that a separate digital filter not be required. By way ofexample, what is known in the digital filter arts as a "root raisedcosine" response is suitable for digital symbol shaping. IF SAW filter915 has such a response. The amplitude versus frequency characteristicof SAW filter 915 is shown in FIG. 1. It has a center frequency at 140mHz and a relatively flat passband of about 24 mHz corresponding to thebandwidth of the received RF signals. A SAW filter with thesecharacteristics utilizing a lithium tantalate substrate is described indetail in U.S. patent application Ser. No. 08/467,095 entitled "SAWFilter for a Tuner of a Digital Satellite Receiver", filed on Jun. 6,1995 for K. J. Richter, M. A. Pugel and J. S. Stewart, and which isassigned to the same assignee as the present application.

In addition, with an IF center frequency of 140 mHz and a RF inputfrequency range between 950 and 1450 mHz, the LO frequency range isbetween 810 and 1310 mHz. The 810-1310 mHz frequency range of the LOsignal permits PLL tuning control ICs which are conventionally andwidely used for broadcast and cable receivers, and therefore relativelyinexpensive, to be used rather than a PLL tuning control ICespecially-designed for satellite receivers. Such a broadcast and cablePLL tuning control IC is the TSA5515T commercially available formPhilips Semiconductors of the Netherlands and others. The maximum LOfrequency available using the TSA5515T and similar ICs is in the orderof 1300 mHz, which is adequate.

The portion of tuning system 9 described so far is the subject matter ofthe above-noted U.S. patent application Ser. No. 08/467,097 entitled"Tuner of a Digital Satellite Receiver" filed on Jun. 6, 1995 for M. A.Pugel and K. J. Richter, and which is also assigned to the same assigneeas the present application. The present invention is specificallyconcerned with provisions for controlling LO 911 during acquisition andfine tuning operation, which will now be described.

The carriers of the RF signals transmitted by the satellite and receivedby antenna 1 have very stable frequencies which remain at "nominal"values. Therefore, as long as the frequency of oscillator 3-5 of LNB 3is stable and remains at its nominal value, the frequencies of cardersof the. RF signals received by tuning system 9 of indoor unit 7 will beat their nominal values. Unfortunately, the frequency of oscillator 3-5can change with time and temperature. The frequency offset of theoscillator 3-5 with respect to its nominal frequency cause correspondingoffsets of carrier frequencies of the RF signals received by tuningsystem 9. To compensate for these frequency offsets, the frequency ofthe LO 911 of tuning system 9 is changed under the control ofmicroprocessor 19 in response to frequency-status information receivedfrom QPSK demodulator during two Search operations. The flow chart ofthe control program of microprocessor 19 for tuning system 9, includingthe search operations, is shown in FIG. 3.

A first search may occur during an acquisition mode after a new programis initially selected. When a new program is selected, microprocessor 19causes the LO frequency to be set to a nominal LO frequencycorresponding to the nominal RF frequency of the transponder for the newprogram. Thereafter, the status of a LOCK signal generated by QPSKdemodulator 11 is monitored. The LOCK signal indicates whether or notQPSK demodulator 11 is operating correctly to demodulate the digitaldata carded by the IF signal. For example, the LOCK signal has a lowlogic level when QPSK demodulator 11 is not properly demodulating thedigital data, and the LOCK signal has a high logic level when QPSKdemodulator 11 is properly demodulating the digital data. If the LOCKsignal has the low logic level after the LO frequency has been set tothe nominal LO frequency for the selected transponder, the frequency ofLO 911 is changed a range surrounding the nominal LO frequency until theLOCK signal has the high logic level. The generation of the LOCK signalindicates the beginning of a steady-state operating mode of tuningsystem 9.

During the steady-state mode, a FREQUENCY signal generated by QPSKdemodulator 11 is monitored to determine whether or not the frequency ofthe carrier of the IF signal is centered within the passband of IF SAWfilter 915, i.e., if the frequency of the carrier of the IF signal is atthe nominal IF center frequency, e.g., 140 mHz in the presentembodiment. The performance of the QPSK demodulator 11 will be degradedand data errors will occur if the frequency of the IF carrier fallsoutside of a predetermined range surrounding the nominal centerfrequency. If the FREQUENCY signal indicates that a predeterminedfrequency offset has not been exceeded, the frequency of LO 911 is leftchanged from the initial value established during the acquisition mode.However, if the FREQUENCY signal indicates that a predeterminedfrequency offset has been exceeded, the frequency of LO 911 is changedduring a, second or "fine tuning" search operation until the situationis corrected. The present invention is directed to solving a problemwhich may occur during the fine tuning mode, as will now be explained.

Tuning system 9, comprising terrestrial broadcast and cable PLL IC 921,has been found to perform very satisfactorily under most circumstances.However, terrestrial tuning PLL IC 921 has certain limitations which mayresult in the temporary loss of video and/or audio information. The sizeof the smallest frequency changes of a local oscillator controlled by aphase locked loop is related to the value of smallest possibleincrements of programmable division factor (N) of programmable divider(÷N) and to the frequency of the reference signal of PLL IC 921.Terrestrial tuning PLL ICs, such as the TSA5515T, are capable ofchanging the frequency of the LO signal only in relatively largeincremental frequency steps, e.g., 62.5 kHz. As a result, during the twosearch operations, the frequency of the carrier of the IF signal willchange in the same relatively large steps. Unfortunately, QPSKdemodulator 11 may not be able to track such relatively large frequencysteps thereby possible causing an interruption of proper demodulationoperation and a loss of video and audio data.

If a first search operation occurs during the acquisition mode, the lossof data is not noticeable because it is expected by a viewer that theacquisition process for a new program will take some time. However,should the second or fine tuning operation become necessary during thesteady-state mode, the video and/or audio responses of the programpresently be viewed may be interrupted. In accordance with an aspect ofthe invention, the possibility of such interruptions is reduced byreducing the "slew rate" of PLL arrangement 919, i.e., the rate at whichthe tuning voltage is allowed to change amplitude, during the finetuning operation. More specifically, the response time of loop filter927 is increased in response to a FINE TUNING control signal generatedby microprocessor 19. The problem to which this aspect of the inventionwill now be described in greater detail with respect to FIGS. 4, whichshows a block diagram of an implementation of QPSK demodulator 11.

As shown in FIG. 4, the IF signal produced by IF SAW filter 915 iscoupled to respective first inputs of mixers 1101I and 1101Q. Theletters "I" and "Q" signify "in-phase" and "quadrature". The outputsignal of a relatively stable frequency oscillator 1103 is directlycoupled to mixer 1101I and indirectly coupled to mixer 1101Q via a 90degree (90° ) phase shift network 1105. Mixer 1101I produces an"in-phase", "near" baseband (much lower frequency) version (IA) of theIF signal, while mixer 1101Q produces an "quadrature", near basebandversion (QA) of the IF signal, which is shifted 90 degrees with respectto the "in-phase" signal (IA). The letter "A" signifies "analog".

The IA and QA signals are coupled to respective analog-to-digitalconverters (ADCs) 1107I and 1107Q. Analog-to-digital converters 1107Iand 1107Q also receive a clock signal from a "timing recovery loop" 1109and produce respective series of digital samples ID and QD. The letter"D" signifies "digital". The frequency and phase of the clock signaldetermines the frequency digital samples and also the phase of thedigital samples of the ID and QD digital signals relative to the IA andQA analog signals. Timing recovery loop 1109 includes a controlledoscillator (not shown) from which the clock signal for ADCs 1107I and1107Q is derived. The controlled oscillator is controlled by a digitalphase locked loop (not shown) so that the digital samples aresynchronized with corresponding amplitude levels of the IA and QA analogsignals, i.e., the maximum and minimum sample values correspond to themaximum and minimum amplitudes of the analog signals. In other words,timing recovery loop 1109 synchronizes the sampling operation of ADCs1107I and 1107Q with the IF signal.

The ID and QD signals are also coupled to a "carrier recovery loop"1111. Carrier recovery loop 1111 demodulates the phase shifts of the IAand QA analog signals represented digital sample signals ID and QD so asto form respective pulse signals IP and QP. The letter "P" signifies"pulse". Each of the IP and QP pulse signals contain a series of pulsescorresponding to data bits. The data bits have either a logic low ("0")level or logic high ("1") level corresponding to 0° and 180° phaseshifts, respectively, of the I and Q signals of the transmitted QPSK RFcarrier. The IP and IQ signal components are coupled to decoder 13,where the various data bits are formatted into MPEG data packets.

Carrier recovery loop 1111 includes a digital phase locked loop (PLL)comprising a controlled oscillator 1111-1, a phase detector 1111-3 and aloop filter 1111-5. Phase detector 1111-3 generates a phase error signalin response to the ID and QD signals and to the output signal ofcontrolled oscillator 1111-1. The nominal frequency and nominal phase ofthe output signal of controlled oscillator 1111-1 corresponds to thenominal frequency and nominal phase of the IF signal and therefore thenominal frequency and phases of IA and QA analog signals and thecorresponding the ID and QD digital sample signals.

In operation, the phase shifts of the signals represented by the ID andQD signals can be reliably determined from the phase error signal if thephase and frequency of the IF signal are correct. However, if the phaseand frequency of the IA and QA are incorrect, the detected phase shiftswill not be at 0° and 180° , but will instead be shifted from thesevalues. In essence, a phase error causes a "tilt" of the "position" oftwo-bit demodulated data with respect to the ideal position of thetwo-bit data in a so called data "constellation" . A frequency error,for example, due to a LNB derived frequency offset of the selected RFsignal, causes a so called "rotation" of the position of the two-bitdemodulated data of the QPSK signal with time. The direction of rotationis dependent on whether the frequency offset is positive or negative. Asis shown in FIG. 4, the data constellation for QPSK modulation has fourpoints corresponding to the four possible logic combinations (00, 01, 10and 11) of the respective two possible logic levels represented by thetwo possible phase shift values of the I and Q signals. Phase detector1111-3 measures the position of the demodulated data relative to theideal position in the data constellation. To correct for data rotationand tilt, the frequency, and thus the phase, of the output signal ofcontrolled oscillator 1111-1 is changed in response to the output signalof phase detector 1111-3 until the rotation stops and the tilt iseliminated. At this point, the demodulated data is reliable and the loopis said to be "locked". A high logic level LOCK signal is generated toindicate that the data is being reliably demodulated and can be decoded.The LOCK signal is generated by examining the derivative of the phaseerror signal to determine when the change in phase error falls below apredetermined limit. As noted above, during the acquisition mode, theLOCK signal is monitored microprocessor 19 and the frequency of LO 911is cause to be adjusted by microprocessor 19 until the LOCK signal has ahigh logic level.

Within limits, the carrier recovery loop 1111 can demodulate the QPSKdata even when the frequency of the IF signal, and therefore thefrequency of the IA and QA signals, is incorrect or offset. However, ifthe frequency offset-is too great, a portion of the frequency spectrumof the IF signal will fall outside of the passband of SAW filter 915 dueto the shift of the IF signal relative to the center frequency of SAWfilter 915. This will cause a degradation of the signal to noise ratioof the receiver. Accordingly, as noted above, microprocessor 19 monitorsa FREQUENCY signal generated by carrier recovery loop 1111 to indicatethe frequency offset of the IF signal. If the frequency offset exceeds apredetermined limit, microprocessor 19 causes the LO frequency to beadjusted to reduce the frequency offset during the ,fine tuning mode.The FREQUENCY signal is generated by integrating the phase errordetected by phase detector 1111-3.

As noted above, the frequency of the LO signal, and therefore thefrequency of the IF signal, changes in relatively large frequency steps,e.g. 62.5 kHz, and it may not be possible for QPSK demodulator 11 totrack such relatively large frequency steps. As a result, aninterruption of proper demodulation operation and a loss of video andaudio data may occur. The ability of QPSK demodulator 11 to track therelatively large frequency changes is a function of the loop bandwidthof carrier recovery loop 1111, and more specifically the response ofloop filter 1111-5. The loop bandwidth of carrier recovery loop 1111should not be made arbitrarily large so as to decrease its response timebecause an increased loop bandwidth would degrade the signal to noisecharacteristics of the receiver and therefore the capability of thereceiver to receive low level signals. It is also not desirable todecrease the loop bandwidth of PLL 919 so as to decrease its responsetime because a decreased response time would result in excessively longacquisition times when new transponder frequencies are selected. Asnoted above, to reduce possibility of the interruption of thedemodulation process during the fine tuning operation, the response timeof tuning control PLL 919 is selectively increased to reduce the rate atwhich the tuning voltage, and therefore the frequency of LO 911, isallowed to change during the fine tuning operation. This solution willnow be described in detail.

Referring back to FIG. 2, and more particularly to the portion of thecircuit labeled "LOOP FILTER 927". As described before, loop filter 927includes amplifier 921-11 within PLL IC 921 and an external filternetwork 925. External filter network 925 includes a first filter stage925-1 and a second, controllable filter stage 925-2 which are coupled incascade between internal amplifier 921-11 and LO 911.

First filter stage 925-1 and amplifier 921-11 pf PLL IC 921 form anintergrator. More specifically, first filter stage 925-1 includes abipolar transistor Q1 arranged as a common-emitter amplifier. The baseof transistor is connected to the output of amplifier 921-11 via an ICterminal. The emitter of transistor Q1 is connected to signal ground. Aload resistor R6 is connected between the collector of transistor Q1 anda source of a supply voltage (÷VCC). A filter section, including aresistor R1 and capacitors C1 and C2, is connected in a negativefeedback path between the collector of transistor Q1 and the input ofamplifier 921-11 via an IC terminal to complete the integrator. Thefeedback is negative due to the signal inversion provided bycommon-emitter configured transistor Q1.

The use of an integrator comprising amplifier 921-1 and first filterstage 925-1 connected in a negative feedback configuration makes PLL 919a type II phase locked loop. A type II phase locked loop minimizes boththe phase and frequency differences between the frequency dividedversion of the LO signal developed at the output of programmablefrequency divider (÷N) 921-3 and the reference frequency signaldeveloped at the output of reference frequency divider (÷R) 921-7, andtherefore stabilizes both the phase and frequency of the LO 911.

Second filter stage 925-2 includes a two double-pole, double-zero filtersection, including resistors R2, R4 and R5 and capacitors C3 and C4, andan electronically controlled switch section comprising field-effecttransistor Q2 and relatively low Value resistor R3. The conduction stateof transistor Q2 is controlled in response to the FINE TUNE signalgenerated by microprocessor 19. Second filter section 925-2 isselectively controlled to either effectively by-pass the double-pole,double-zero filter section (R2, R4, R5, C3 and C4), or to include thedouble-pole, double-zero filter section in the path between first filtersection 925-1 and LO 911. More specifically, when tuning system 9 is notin the fine tuning mode of operation, the FINE TUNE signal has a lowlogic level and the conduction channel of transistor Q2 is caused to bein the low impedance state, or "on". As a result, elements resistors R2,R4 and R5 and capacitors C3 and C4 of second filter section 925-2 areeffectively by-passed due to "on" transistor Q2 and relatively low valueresistor R3. In the fine tuning mode, the FINE TUNE signal has a highlogic level and the conduction channel of transistor Q2 is caused to bein the high impedance state, or "off". As a result, resistors R2, R4 andR5 and capacitors C3 and C4 of second filter section 925-2 are connectedin the path between first filter section 925-1 and LO 911.

The Bode amplitude versus frequency characteristic for double-zerofilter section (R2, R4, R5, C3 and C4) of second filter stage 925-2 byitself is shown in Figure as characteristic #1. Amplitudes levels areindicated in decibels (dB) and the frequency axis is logarithmic.Characteristic #1 is seen to contain two "poles" P1 and P2 and two"zeros" Z1 and Z2, which occur in the order: pole P1, zero Z1, zero Z2and pole P2 at successively higher frequencies. Pole P1 is due toresistor R2 and capacitor C4; zero Z1 is due to resistor R2 andcapacitor C3; zero Z2 is due to resistor R5 and capacitor C4; and poleP2 is due to resistor R5 and capacitor C-3.

Two Bode amplitude versus frequency characteristics of the overall loopresponse of PLL 919 are also shown in FIG. 5. Characteristic #2 is theloop response when tuning system 9 is not in the fine tuning mode andloop filter 927 includes only first filter stage 925-1, i.e., thedouble-pole, double-zero filter section (R2, R4, R5, C3 and C4) ofsecond filter stage 925-2 is by-passed. Characteristic #3 is the loopresponse when tuning system 9 is in the fine tuning mode and loop filter927 includes first filter stage 925-1 and the double-pole, double-zerofilter section (R2, R4, R5, C3 and C4) of second filter stage 925-2coupled in cascade. Characteristic #2 has not been drawn to scale interms of amplitude with respect to characteristics #1 and #2 to avoid anoverlap of the characteristics.

Recalling that the overall amplitude versus frequency characteristic oftwo stages connected in cascade results is the multiplicative product ofthe two individual characteristics, or the additive product whenamplitudes are expressed in decibel (dB) levels, characteristic #3results from the additive combination of characteristics #1 and 2. Apole of characteristic #1 causes an increase of the slope (in thenegative direction) of characteristic #3. A zero of characteristic #1causes a decrease of the slope (in the negative direction) ofcharacteristic #3. Pole P1 reduces the overall loop gain and thereby theoverall loop bandwidth. Without zeros Z1 and Z2, the slope ofcharacteristic #3 would cross the 0 dB amplitude level with a slope ofgreater than 20 dB per decade of frequency, causing the loop to beunstable and thereby subject to oscillations. Pole P2 occursincidentally due to the circuit topology requiring resistor R5 andcapacitor C3. Nevertheless, pole P2 is advantageous in that it reducesthe loop gain (i.e., increases the attenuation) for out-of-band signalssuch as the reference frequency signal of PLL 919.

It is seen in FIG. 5 that when tuning system 9 is not in the fine tuningmode (characteristic #2) the loop bandwidth is relatively large andtherefore the response of PLL 919 is relatively fast. In contrast, whentuning system 9 is in the fine tuning mode (characteristic #3) the loopbandwidth is relatively small and therefore the response of PLL 919 isrelatively slow.

In the implementation of second filter stage 925-2 shown in FIG. 2,resistor R4 is desirable to isolate the output of first filter stage925-1 (at the collector of transistor Q1) from capacitor C4 for thefollowing reasons. Capacitor C4 has a relatively large capacitance.Without resistor R4 (i.e., if resistor R4 were replaced by a directconnection), the series connection of capacitor C4 and resistor R5 wouldbe directly connected in shunt with the output of first filter stage925-1 when the tuning system is in the acquisition mode and switchingtransistor is "on". This would tend to undesirably increase theacquisition time. However, relatively high value resistor R4 isolatesthe output of first filter stage 925-1 from capacitor C4 and therebyinhibits capacitor C4 from significantly increasing the acquisitiontime.

Further in regard to relatively high valued capacitor C4, it may bedesirable to provide for a predetermined time delay before allowing thefine tuning operation to begin after the acquisition mode to allowcapacitor C4 to charge (or discharge) to the tuning voltage generatedduring the acquisition operation. Such a delay can be provided bymicroprocessor 19 under program control, as is indicated in the flowchart shown in FIG. 3.

It may be desirable to add a dynamic "speed-up" circuit 925-3 to firstfilter stage 925-1 as is shown in FIG. 2 to change the response time ofPLL 919 so as to speed up the acquisition operation. Speed-up circuit925-3 includes push-pull configured opposite conductivity type bi-polartransistors Q3 and Q4 and a resistor R7. The commonly connected bases oftransistors Q3 and Q4 are connected to one side of Capacitor C1 and thecommonly connected emitters are connected via resistor R7 to the otherside of capacitor C1. The collectors of transistors Q3 and Q4 areconnected to respective sources of opposite polarity supply voltages÷VCC and -VCC.

Exemplary component values for external filter network 925 are indicatedin the following table.

    ______________________________________                                        Component        Value                                                        ______________________________________                                        resistor R1      24     K (kiloohms)                                          capacitor C1     4700   pf (picofarads)                                       capacitor C2     0.1    μf (microfarads)                                   resistor R6      2      K                                                     resistor R7      10     K                                                     resistor R2      1      M (megaohms)                                          capacitor C3     0.27   μf                                                 resistor R3      2      K                                                     resistor R4      20     K                                                     resistor R5      470    ohms                                                  capacitor C5     220    μf                                                 ______________________________________                                    

In operation, when a large frequency change occurs, such as when a newtransponder frequency is selected, a large error signal is generated anda corresponding large voltage is developed across resistor R1. Dependingon the polarity of the change, one of transistors Q3 or Q4 turns "on"and "sources" or "sinks" current. This causes an effective increase inthe loop gain (i.e., characteristic #2 is shifted upward) and aconsequential decrease in acquisition time. As PLL 919 nears the desiredfrequency and the error signal decreases, the "on" transistor is turned"off". A speed-up circuit similar to speed-up circuit 925-3, as well asother speed-up circuits, are described in detail in U.S. patentapplication Ser. No. 08/504,849, entitled "Fast Acting Control System",filed on Jul. 20, 1995 for David M. Badger, and assigned to the sameassignee as the present application.

While the invention has been described by way of example in terms of aspecific embodiment for a particular application, it will be appreciatedby those skilled in the art that modifications may be made to suit otherapplications. For example, the invention is not limited to use in atuning system for a satellite receiver and may be employed whenever thestep size of the local oscillator is relatively large with respect tothe tracking capability of the carrier recovery loop. In addition, whilethe invention has been described in terms of receiver in which theresponse time of the tuning control phase locked loop is increasedduring the fine tuning mode to selectively change the relative responsetimes of the tuning control phase locked loop and the carrier recoveryloop during the fine tuning mode to allow the carrier recovery loop totrack frequency changes of said IF signal due to frequency changes ofthe local oscillator and thereby maintain proper demodulation of said IFsignal, it is possible to decrease the response time of the carrierrecovery loop during the fine tuning mode. However, increasing theresponse time of the tuning control phase locked loop is consideredpreferable, because, as noted above, decreasing the response time of thecarrier recovery loop may cause a degradation of the video and audioresponses due to a decrease in the signal to noise performance of thedemodulator. Further, while the invention has been described withrespect to a system which employs a carrier recovery loop fordemodulating a QPSK modulated carrier, the invention is also applicableto systems which employ carrier recovery loops for demodulating carriersmodulated with digital data in ways, such as QAM (quadrature amplitudemodulation). These and other modifications are intended to be within thescope of the invention defined by the following claims.

We claim:
 1. Apparatus for processing digital signals modulated on toones of a plurality of RF carrier signals, comprising:a RF input forreceiving said plurality modulated RF carrier signals;. a tuning controlphase locked loop including a local oscillator for generating a localoscillator signal; a mixer coupled to said RF input and to said localoscillator for producing an IF signal modulated with digital signalscorresponding to a selected RF signal of said plurality of RF signals;an IF filter having a center frequency; said IF signal having a nominalfrequency corresponding to said center frequency of said IF filter; adigital signal demodulator including a carrier recovery loop means fordemodulating said IF to produce said digital signals carried by said IFsignal; and means for controlling the operation of said tuning controlphase locked loop in response to at least one control signal generatedby said carrier recovery loop which indicates the status of operation ofsaid carrier recovery loop; said controlling means controlling saidtuning control phase locked loop to (1) establish an initial localoscillator frequency corresponding to said selected RF signal during anacquisition mode starting when said selected RF signal is initiallyselected and ending when said second closed loop is properlydemodulating said IF signal, and (2) change the local oscillatorfrequency from said initial local oscillator frequency to a reduce afrequency offset of said IF signal from said nominal IF frequency duringa fine tuning mode; said controlling means further selectively changingthe relative response times of said tuning control phase locked loop andsaid carrier recovery loop during said fine tuning mode to allow saidcarrier recovery loop to track frequency changes of said IF signal dueto changes of said local oscillator frequency and thereby maintain theproper demodulation of said IF signal.
 2. The apparatus recited in claim1, wherein:the frequency of said local oscillator is changed in stepslarge enough during said fine tuning mode to temporarily interrupt theproper demodulation of said IF signal by said digital demodulator due tothe inability of said carrier recovery loop to quickly enough track saidlarge step changes of the frequency of said local oscillator.
 3. Theapparatus recited in claim 1, wherein:said RF signals have frequencieswhich is greater than the frequency range used for conventionalterrestrial broadcast and cable television transmissions; and said phaselocked loop means comprises a phase locked loop tuning controlintegrated circuit normally employed in a terrestrial broadcast andcable television receiver.
 4. The apparatus recited in claim 3,wherein:said RF input is adapted to receive said RF signal from a blockconverter which is capable of offsetting the frequencies of said RFcarrier signals form respective nominal frequencies.
 5. The apparatusrecited in claim 1, wherein:said RF signals are QPSK modulated with saiddigital signals; and said demodulator is a QPSK demodulator.
 6. Theapparatus recited in claim 1, wherein:said controlling means increasesthe response time of said tuning control phase locked loop during saidfine tuning mode.
 7. The apparatus recited in claim 6, wherein:saidtuning control phase locked loop includes a controllable filter whichdetermines the response time of said tuning control phase locked loop;and said controlling means controls said filter for to increase theresponse time of said tuning control phase locked loop during said finetuning mode.
 8. The apparatus recited in claim 7, wherein:said filterincludes first and second filter stages; and said controlling meanscontrols said second filter section to increase the response time ofsaid first closed loop means during said fine tuning mode.
 9. Theapparatus recited in claim 8, wherein:said local oscillator isresponsive to a tuning control signal which determines its frequency ofoscillation; said first closed loop includes means for comparing thefrequency of oscillation of said local oscillator to a reference valueto generate an error signal; said filter is coupled to said comparingmeans for filtering said error signal to produce said tuning controlsignal for said local oscillator; said first and second filter stagesare coupled in cascade between said comparing means and said localoscillator; and said second filter stage includes a filter section and aswitching section for selectively bypassing and said filter section ofsaid second filter stage under the control of said controlling means.10. The apparatus recited in claim 9, wherein:said comparing means iscoupled to said filter means via an amplifier; and said first filterstage includes an a filter section which is coupled in a negativefeedback configuration with said amplifier.
 11. Apparatus for processingdigital signals modulated on to ones of a plurality of RF carriersignals, comprising:a RF input for receiving said plurality modulated RFcarrier signals; a first closed loop means including a local oscillatorfor generating a local oscillator signal; a mixer coupled to said RFinput and to said local oscillator for producing an IF signal modulatedwith digital signals corresponding to a selected RF signal of saidplurality of RF signals; an IF filter having a center frequency; said IFsignal having a nominal frequency corresponding to said center frequencyof said IF filter; a digital signal demodulator including a secondclosed loop means for demodulating said IF to produce said digitalsignals carried by said IF signal; and means for controlling theoperation of said first closed loop means in response to at least onecontrol signal generated by said second closed loop means whichindicates the status of operation of said second closed loop means; saidcontrolling means controlling said first closed loop means to (1)establish an initial local oscillator frequency corresponding to saidselected RF signal during an acquisition mode starting when saidselected RF signal is initially selected and ending when said secondclosed loop is properly demodulating said IF signal, (2) maintain saidinitial local oscillator frequency during a steady-state mode, and (3)change the local oscillator frequency from said initial local oscillatorfrequency to a reduce a frequency offset of said IF signal from saidnominal IF frequency during a fine tuning mode; said controlling meansfurther controlling said first closed loop means to increase theresponse time of said first closed locked loop means to allow saidsecond closed loop means to track frequency changes of said IF signaldue to frequency changes of said local oscillator and thereby maintainthe proper demodulation of said IF signal during said fine tuning mode.12. The apparatus recited in claim 11, wherein:said RF signals havefrequencies which is greater than the frequency range used forconventional terrestrial broadcast and cable television transmissions;and said first close loop means comprises a phase locked loop tuningcontrol integrated circuit normally employed in a terrestrial broadcastand cable television receiver.
 13. The apparatus recited in claim 11,wherein:said RF input is adapted to receive said RF signal from a blockconverter which is capable of offsetting the frequencies of said RFcarrier signals form respective nominal frequencies.
 14. The apparatusrecited in claim 11, wherein:said first closed loop means is a phaselocked loop; and said second closed loop means is a carrier recoveryloop.
 15. The apparatus recited in claim 14, wherein:said RF signals areQPSK modulated with said digital signals; and said demodulator is a QPSKdemodulator.
 16. The apparatus recited in claim 11, wherein:said firstcontrol loop means includes a controllable filter which determines theresponse time of said first close loop means; and said controlling meanscontrols said filter for to increase the response time of said firstclosed loop means during said fine tuning mode.
 17. The apparatusrecited in claim 16, wherein:said filter includes first and secondfilter stages; and said controlling means controls said second filtersection to increase the response time of said first closed loop meansduring said fine tuning mode.
 18. The apparatus recited in claim 17,wherein:said local oscillator is responsive to a tuning control signalwhich determines its frequency of oscillation; said first closed loopincludes a means for comparing the frequency of oscillation of saidlocal oscillator to a reference value to generate an error signal; saidfilter is coupled to said comparing means for filtering said errorsignal to produce said tuning control signal for said local oscillator;said first and second filter stages are coupled in cascade between saidcomparing means and said local oscillator; and said second filter stageincludes a filter section and a switching section for selectivelybypassing and said filter section of said second filter stage under thecontrol of said controlling means.
 19. The apparatus recited in claim18, wherein:said comparing means is coupled to said filter means via anamplifier; and said first filter stage includes a filter section whichis coupled in a negative feedback configuration with said amplifier soas to form an integrator; said comparing means and said amplifier areincluded in an integrator circuit; said filter section of said firstfilter stage, said filter section of said second filter stage areexternal to said integrated circuit.
 20. Apparatus for processingdigital signals modulated on to ones of a plurality of RF carriersignals, comprising:a RF input for receiving said plurality modulated RFcarrier signals; a first closed loop means including a local oscillatorfor generating a local oscillator signal; a mixer coupled to said RFinput and to said local oscillator for producing an IF signal modulatedwith digital signals corresponding to a selected RF signal of saidplurality of RF signals; an IF filter having a center frequency; said IFsignal having a nominal frequency corresponding to said center frequencyof said IF filter; a digital signal demodulator including a secondclosed loop means for demodulating said IF to produce said digitalsignals carried by said IF signal; and means for controlling theoperation of said first closed loop means in response to at least onecontrol signal generated by said second closed loop means whichindicates the status of operation of said second closed loop means; saidcontrolling means controlling said first closed loop means to (1)establish an initial local oscillator frequency corresponding to saidselected RF signal during an acquisition mode starting when saidselected RF signal is initially selected and ending when said secondclosed loop is properly demodulating said IF signal, (2) maintain saidinitial local oscillator frequency during a steady-state mode, and (3)change the local oscillator frequency from said initial local oscillatorfrequency to a reduce a frequency offset of said IF signal from saidnominal IF frequency during a fine tuning mode; said first closed loopmeans having a first response time during said acquisition mode, asecond response time greater than said first response time during asteady state mode, and a third response time greater than said secondresponse time during said fine tuning mode.